The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which can aid in removing defects produced when forming capacitors and thereby protect against various DC failures.
In high integration configurations of DRAM (dynamic random access memory) semiconductor devices, a great deal of effort has been expended to secure adequate space for the capacitors within the confines of the diminutive compact cells.
Generally these methods of compacting the capacitors capacity have included using extremely high dielectric constant materials for the interfacial dielectric layer of the capacitors, decreasing the thickness of the dielectric layer of capacitor, and/or increasing the effective area of a storage electrode of capacitor.
Among these methods, increasing the effective area of a storage electrode is most commonly chosen option to increase the capacity given the restricted choice of the existing dielectric material and the physical limitations on how thick the dielectric layer can be.
Usually, increasing the effective area of a storage electrode involves designing a three-dimension shape, such as a cylinder, and extending the height of this three-dimension shape to increase the area of the storage electrode.
FIGS. 1 through 4 depict sectional views illustrating some of the more conventional methods for manufacturing a semiconductor device and explaining problems caused therein.
Referring now to FIG. 1, a first interlayer dielectric 11 is shown formed on a substrate 10 which has a cell region CELL and a peripheral region PERI. Storage node contacts 12 are formed through the first interlayer dielectric 11 and electrically couple with the substrate 10 in the cell region CELL.
While not shown in the drawing, it is understood that the substrate 10 can include any number of various underlying structures such as an isolation layer, gates, bit lines, and so forth.
In succession, storage electrodes 13 are formed on the storage node contacts 12 in the shape of cylinders. A dielectric layer 14 and a plate electrode 15 are deposited in the cell region CELL including the storage electrodes 13 and in the peripheral region PERI, and then, the plate electrode 15 and the dielectric layer 14 which are formed in the peripheral region PERI are removed. As a consequence, capacitors, each of which is composed of the storage electrode 13, the dielectric layer 14 and the plate electrode 15, are formed within the cell region CELL.
Next, a second interlayer dielectric 16 is formed in the cell region CELL and the peripheral region PERI.
Due to the presence of the capacitors formed in the cell region CELL, the second interlayer dielectric 16 is formed such that it has a step portion between the cell region CELL and the peripheral region PERI.
Referring now to FIG. 2, the second interlayer dielectric 16 is subsequently planarized by for instance being polished down using a CMP (chemical mechanical polishing) planarizing process.
Referring now to FIG. 3, a contact plug 17 is formed through the second and first interlayer dielectrics 16 and 11 in the peripheral region PERI to be electrically coupled to the substrate 10. A metal layer is then formed in the cell region CELL and the peripheral region PERI, and metal lines 18 are subsequently formed by selectively patterning the metal layer using a photolithographic process.
In the conventional method, a problem can arise in that the defects DEFECT are prone to being produced subsequent to forming the capacitors by being exposed when conducting the CMP process that planarizes the second interlayer dielectric 16. As a result, short circuits, i.e., DC failures, can occur between the capacitors and the metal lines 18 or between various metal lines 18 due to these defects DEFECT. Furthermore the CMP process can produce scratches on the surface of the second interlayer dielectric 16 in which the subsequently deposited metal layer can preserve these scratches. The metal line 18 made from the deposited metal layer having the preserved scratches can also result in producing unwanted short circuits, i.e., DC failures, between the various metal lines 18.
In order to protect against these types of DC failures, a method, as shown in FIG. 4, has been proposed in which a third interlayer dielectric 19 is additionally formed on the second interlayer dielectric 16 after the CMP process is used to planarize the second interlayer dielectric 16.
However, in this third interlayer dielectric method, the third interlayer dielectric 19 results in the need to heighten the contact plug 17 formed in the peripheral region PERI, and as a result the resistance of the contact plug 17 is prone to increasing. Further, when defining a contact hole for forming the contact plug 17 through etching, the contact hole is likely to be insufficiently opened, whereby the reliability of a semiconductor device can deteriorate.